---
product_id: 113352119
title: "RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design"
price: "₩7947"
currency: KRW
in_stock: false
reviews_count: 12
url: https://www.desertcart.kr/products/113352119-rtl-modeling-with-systemverilog-for-simulation-and-synthesis-using-systemverilog
store_origin: KR
region: South Korea
---

# RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design

**Price:** ₩7947
**Availability:** ❌ Out of Stock

## Quick Answers

- **What is this?** RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design
- **How much does it cost?** ₩7947 with free shipping
- **Is it available?** Currently out of stock
- **Where can I buy it?** [www.desertcart.kr](https://www.desertcart.kr/products/113352119-rtl-modeling-with-systemverilog-for-simulation-and-synthesis-using-systemverilog)

## Best For

- Customers looking for quality international products

## Why This Product

- Free international shipping included
- Worldwide delivery with tracking
- 15-day hassle-free returns

## Description

*** Purchase the paperback book, and get the Kindle ebook for just $2.99 using the Matchbook price! *** This book is both a tutorial and a reference for engineers who use the SystemVerilog Hardware Description Language (HDL) to design ASICs and FPGAs. The book shows how to write SystemVerilog models at the Register Transfer Level (RTL) that simulate and synthesize correctly, with a focus on proper coding styles and best practices. SystemVerilog is the latest generation of the original Verilog language, and adds many important capabilities to efficiently and more accurately model increasingly complex designs. This book reflects the SystemVerilog-2012/2017 standards. The audience for this book is for engineers who already know, or who are learning, digital design engineering. The book does not present digital design theory; it shows how to apply that theory to write RTL models that simulate and synthesize correctly. (Note: This book provides a more comprehensive examination of the RTL modeling aspects of SystemVerilog than the author's older "SystemVerilog for Design" book. The older book was written for an audience that already knows the Verilog-2001 language and only presents the extensions that SystemVerilog adds to Verilog-2001. This book covers the full, combined Verilog and SystemVerilog language, with more emphasis on best coding styles for simulation and synthesis.) The creator of the original Verilog Language, Phil Moorby says about this book (excerpt from the book's Foreward): “Many published textbooks on the design side of SystemVerilog assume that the reader is familiar with Verilog, and simply explain the new extensions. It is time to leave behind the stepping-stones and to teach a single consistent and concise language in a single book, and maybe n much mot even refer to the old ways at all! If you are a designer of digital systems, or a verification engineer searching for bugs in these designs, then SystemVerilog will provide you with significant benefits, and this book is a great place to learn the design aspects of SystemVerilog.” About the Author: Stuart Sutherland provides expert SystemVerilog training workshops and consulting services. Stuart has more than 30 years of experience with Verilog and SystemVerilog. He has served as the technical editor for every version of the IEEE Verilog and SystemVerilog Language Reference Manuals (LRMs). Stuart founded Sutherland HDL, Inc. in 1992, located in Tualatin, Oregon, USA. Stuart has authored and co-authored numerous papers on these languages (available at www.sutherland-hdl.com). He has authored the books: “The Verilog PLI Handbook”,“Verilog-2001: A Guide to the New Features of the Verilog HDL, and “SystemVerilog for Design: A Guide to Using the SystemVerilog Enhancements to Verilog for Hardware Design” (co-authored with Simon Davidmann and Peter Flake), and "Verilog and SystemVerilog Gotchas:101 Common Coding Error and How to Avoid Them" (co-authored with Don Mills)”. Stuart holds a Bachelor’s Degree in Computer Science with an emphasis in Electronic Engineering Technology from Weber State University (Ogden, Utah) and Franklin Pierce College (Nashua, New Hampshire), and a Master’s Degree in Education with an emphasis on eLearning course development from Northcentral University (Prescott, Arizona).

Review: Excellent reference for RTL designers - While the title of this book says it's "for Simulation and Synthesis", the emphasis in the text is clearly on the latter. Mr. Sutherland (who tragically passed away suddenly in 2018) has long advocated for the synthesis features of SystemVerilog in his conference papers and training seminars. This is more than just an update to Mr. Sutherland's earlier book, "SystemVerilog for Design". The earlier book focused mainly on how SystemVerilog differed from the original Verilog language, and its target audience was experienced Verilog designers looking to understand and take advantage of the new SystemVerilog features. This new book dispenses with most of that (but not all), and details SystemVerilog as though the reader is not already familiar with Verilog. However, I can't assess how well this book serves a reader who is completely new to SystemVerilog or HDL-based design. As one who has used Verilog since 1994 and SystemVerilog since 2012, for both synthesis and simulation of FPGAs, I found this book to be extremely useful and readable, and I picked up a number of language features and "tricks" which I wasn't previously aware of. I especially liked how he summarizes the key principles of each chapter at the end, and the numerous "Best Practice Guides" distributed throughout the text with recommendations--and explanations--based on real-world use. It has a thorough index, which is also important for use as a reference. I also recommend, as a companion reference, Chris Spear's also excellent "SystemVerilog for Simulation".
Review: Best SystemVerilog book out there - This book is up to date and comprehensive. Love the best practices advice in each section. Not just the best SystemVerilog book, but one of the best hardware modeling books out there.

## Technical Specifications

| Specification | Value |
|---------------|-------|
| Best Sellers Rank | #713,910 in Kindle Store ( See Top 100 in Kindle Store ) #26 in Digital Design (Kindle Store) #69 in Digital Design (Books) |

## Images

![RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design - Image 1](https://m.media-amazon.com/images/I/8119+4ku4gL.jpg)

## Customer Reviews

### ⭐⭐⭐⭐⭐ Excellent reference for RTL designers
*by M***N on March 3, 2019*

While the title of this book says it's "for Simulation and Synthesis", the emphasis in the text is clearly on the latter. Mr. Sutherland (who tragically passed away suddenly in 2018) has long advocated for the synthesis features of SystemVerilog in his conference papers and training seminars. This is more than just an update to Mr. Sutherland's earlier book, "SystemVerilog for Design". The earlier book focused mainly on how SystemVerilog differed from the original Verilog language, and its target audience was experienced Verilog designers looking to understand and take advantage of the new SystemVerilog features. This new book dispenses with most of that (but not all), and details SystemVerilog as though the reader is not already familiar with Verilog. However, I can't assess how well this book serves a reader who is completely new to SystemVerilog or HDL-based design. As one who has used Verilog since 1994 and SystemVerilog since 2012, for both synthesis and simulation of FPGAs, I found this book to be extremely useful and readable, and I picked up a number of language features and "tricks" which I wasn't previously aware of. I especially liked how he summarizes the key principles of each chapter at the end, and the numerous "Best Practice Guides" distributed throughout the text with recommendations--and explanations--based on real-world use. It has a thorough index, which is also important for use as a reference. I also recommend, as a companion reference, Chris Spear's also excellent "SystemVerilog for Simulation".

### ⭐⭐⭐⭐⭐ Best SystemVerilog book out there
*by A***P on March 3, 2021*

This book is up to date and comprehensive. Love the best practices advice in each section. Not just the best SystemVerilog book, but one of the best hardware modeling books out there.

### ⭐⭐⭐⭐⭐ Great System Verilog RTL syntax and best practices overview
*by S***D on December 30, 2021*

Great book. Using it as a reference to switch to system verilog from VHDL. Only complaint is that the ordering of topics could be different to be more natural: put in conditionals/cases and clocked processes right after the overview of ports. Other than that, it's made the transition very straight forward.

---

## Why Shop on Desertcart?

- 🛒 **Trusted by 1.3+ Million Shoppers** — Serving international shoppers since 2016
- 🌍 **Shop Globally** — Access 737+ million products across 21 categories
- 💰 **No Hidden Fees** — All customs, duties, and taxes included in the price
- 🔄 **15-Day Free Returns** — Hassle-free returns (30 days for PRO members)
- 🔒 **Secure Payments** — Trusted payment options with buyer protection
- ⭐ **TrustPilot Rated 4.5/5** — Based on 8,000+ happy customer reviews

**Shop now:** [https://www.desertcart.kr/products/113352119-rtl-modeling-with-systemverilog-for-simulation-and-synthesis-using-systemverilog](https://www.desertcart.kr/products/113352119-rtl-modeling-with-systemverilog-for-simulation-and-synthesis-using-systemverilog)

---

*Product available on Desertcart South Korea*
*Store origin: KR*
*Last updated: 2026-06-03*